1. Technical Field
The present disclosure relates to a circuit for enabling a sense amplifier in a semiconductor memory device and, more particularly, to a circuit for enabling a sense amplifier in a semiconductor memory device that is capable of adjusting an enable time of the sense amplifier according to a temperature change.
2. Discussion of Related Art
In fabricating an MOS transistor, a large isolation region is generally formed to provide isolation between devices and to prevent a latch-up phenomenon in the MOS transistor. In this case, the isolation region increases the area of a chip and degrades integration. Silicon on insulator (SOI) has been conventionally suggested to solve such problems.
The SOI is a technique of more efficiently isolating semiconductor devices formed on a silicon substrate, and has a structure in which a mono-crystalline silicon layer is laid on an insulating layer. Because the SOI structure has a thin insulating layer buried between a surface of a wafer, which forms a circuit, and an under layer, the SOI is more robust against light and a high supply voltage, as compared to a junction isolation structure. Advantageously, a device formed on SOI requires a smaller number of processes than a device formed on a bulk silicon layer and has less capacitive coupling between devices formed in a chip.
When devices are formed on both a lower bulk silicon layer and an upper mono-crystalline silicon layer, a resultant structure has a stacked solid form. Accordingly, a semiconductor memory device having this structure is defined as a semiconductor memory device of a stack type. For example, if a memory cell of an SRAM is formed, the SRAM having that structure is defined as an SRAM of a stack type.
Examples of a semiconductor memory device having the SOI are disclosed in U.S. Pat. Nos. 6,060,738 and 6,288,949.
When a memory cell is formed on the SOI, it may be inferior in operation to a memory cell formed on a bulk silicon layer due to its structural features, for example, a back bias voltage (VBB) is allowed to be applied to the device formed on a lower bulk silicon, but not to the device formed on the SOI.
In particular, in conventional memory cells formed on a bulk silicon substrate, since a temperature decrease leads to performance improvement of a transistor, pulse width or sensing time reduction due to a temperature decrease is not problematic.
In the memory cells formed on SOI, however, a delay reduction at the transistor due to temperature increase may be problematic.
In addition, when the bulk silicon is used with the SOI, a control circuit for controlling a delay at the transistors is needed, since the delay according to the temperature may differ.
FIG. 1 is a circuit diagram showing a conventional sense amplifier enabling circuit.
Referring to FIG. 1, a conventional semiconductor memory device includes a memory cell 2, a sense amplifier 4, and a sense amplifier enabling circuit 6.
In a read operation of the semiconductor memory device, data dat a and data dat aB stored in the memory cell 2 are transferred to a pair of bit lines corresponding to the memory cell 2. The data dat a and dat aB are sensed and amplified by the sense amplifier 4 and then output along a read path RD. Typically, a word line connected to the memory cell 2 needs to be first selected by a row address decoder (not shown).
A sensing margin of the pair of bit lines should be sufficient from a time point at which the word line connected with the memory cell 2 is selected to a time point at which the sense amplifier 4 is enabled, that is, a sense amplifier enable signal is applied. This is shown in the timing diagram of FIG. 2 and, thus, will be described with reference to FIG. 2.
The sense amplifier enabling circuit 6 receives an externally applied sense amplifier enable signal SA_EN. The sense amplifier enabling circuit 6 generates a sense amplifier enable delay signal DSA_EN and applies it to the sense amplifier 4. The sense amplifier enabling circuit 6 includes one or more inverters INV1, INV2, INV3, and INV4. The sense amplifier enable delay signal DSA_EN is a signal obtained by delaying the sense amplifier enable signal SA_EN for a predetermined time at the sense amplifier enabling circuit 6.
For example, the inverter INV1 includes a PMOS transistor PM1 and an NMOS transistor NM1. Gates of the PMOS transistor PM1 and the NMOS transistor NM1 are connected to each other. A power voltage VCC is applied to a source of the PMOS transistor PM1, and a source of the NMOS transistor NM1 is grounded. Drains of the PMOS transistor PM1 and the NMOS transistor NM1 are connected to each other, and a connection between the drains is an output terminal of the inverter INV1. While only one inverter INV1 has been described by way of example, the other inverters INV2, INV3, and INV4 have the same configuration as the inverter INV1. The number of inverters may be variously changed.
The sense amplifier enabling circuit 6 is generally formed on a bulk silicon layer. When the memory cell 2 is formed on the bulk silicon, performance of a memory cell is improved as the temperature decreases, and the sensing time correspondingly decreases. In a semiconductor memory device having a memory cell formed on SOI or a memory cell having an opposite tendency according to temperature relative to a conventional memory cell, however, the use of a sense amplifier enabling circuit formed on a bulk silicon layer, as in the prior art, causes the following problems.
First, if the sense amplifier enabling circuit is configured in consideration of a sensing time and a sensing margin at a high temperature, a failure is caused because the performance of the memory cell is degraded as the temperature decreases.
On the contrary, if the sense amplifier enabling circuit is configured in consideration of the sensing time and the sensing margin at a low temperature, the sensing is made relatively excellent due to the performance of the memory cell being improved as the temperature increases. Since a delay amount in the sense amplifier enabling circuit at a high temperature is greater than an actually required amount than at a low temperature, however, the cycle time is reduced.
FIG. 2 is a timing diagram illustrating the sensing margin and the sensing time present in the circuit shown in FIG. 1.
Referring to FIG. 2, a timing diagram of a pair of bit lines BL and BLB and a sense amplifier enable delay signal DSA_EN is shown.
The pair of bit lines BL and BLB are lines via which the data dat a and dat aB are transferred from the memory cell to the sense amplifier in FIG. 1. Accordingly, the pair of bit lines BL and BLB may be considered as the lines indicated as dat a and dat aB in FIG. 1.
The sense amplifier enable delay signal DSA_EN is a signal obtained by delaying the sense amplifier enable signal SA_EN by the sense amplifier enabling circuit 6, as described above.
The reference character t1 indicates the sensing time and the reference character m1 indicates the sensing margin. The sensing time t1 refers to a period of time from a time at which the word line is enabled to a time at which the sense amplifier is enabled by a sense amplifier enable signal. The sensing margin m1 refers to a minimal width within which the enabled sense amplifier can sense and amplify data on the pair of bit lines BL and BLB.
When the data in the memory cell is loaded on the pair of bit lines BL and BLB after the word line (not shown) is selected, the pair of bit lines BL and BLB will have a predetermined sensing margin m1. Since the sensing margin m1 is a minimal width that allows the enabled sense amplifier to sense and amplify data on the pair of bit lines BL and BLB, the sense amplifier enable signal SA_EN needs to be applied at a time point when the sensing margin is greater than the sensing margin m1. That is, the sense amplifier enable signal SA_EN has to be applied after the sensing time t1 lapses, such that a sensing failure does not occur.
The sensing margin and sensing time vary with temperature. This will be described with reference to FIG. 3.
FIG. 3 is a timing diagram illustrating the sensing margin and sensing time according to the temperature in the sense amplifier enabling circuit of FIG. 1
Referring to FIG. 3, the sensing margin and the sensing time varying with temperature are shown. The sensing margin m1 and the sensing time t1 are values present at a normal temperature, and a sensing margin m2 is sensed in a sensing time t2. When a sense amplifier enabling circuit is formed on a bulk silicon layer, the current driving capability of the transistors constituting the sense amplifier enabling circuit is improved as the temperature decreases, such that a delay at the sense amplifier enabling circuit decreases. Accordingly, the sensing time t2 is smaller than the sensing time t1. A sensing margin m3 indicates a minimum width of data that can be sensed by the sense amplifier. The sensing time t3 is a time needed to reach the sensing margin m3 and is greater than the normal sensing time t1.
For example, in a semiconductor memory device having a memory cell formed on an SOI, current driving capability of transistors constituting the memory cell is degraded when the temperature decreases. Accordingly, the sensing margin m2 at the sensing time t2 is smaller than the sensing margin m1, as described above. In this case, a failure occurs in the read operation of the semiconductor memory device.
In this case, if the sensing margin is to be greater than m3 in order to prevent a failure from occurring, the sensing time has to increase to t3. That is, the sense amplifier enabling circuit needs to additionally delay the sense amplifier enable signal by t3-t1 in addition to the normal sensing time t1.
In this manner, in the case of a typical memory cell formed on the bulk silicon layer, the current driving capability of a transistor constituting the memory cell increases as the temperature decreases. Accordingly, a decrease of the sensing time t1 to the sensing time t2 is not problematic. This is because the sensing margin increases correspondingly.
In the case of a memory cell formed on an SOI, however, since the current driving capability of a transistor constituting the cell is degraded as the temperature decreases, the sensing time needs to increase in order to obtain a sensing margin allowing the sense amplifier to sense and amplify data on the pair of bit lines.